1. Field of the Invention
This invention relates to a semiconductor integrated circuit device and relates in particular to a semiconductor integrated circuit device having a high speed clock distribution network. This invention further relates to a technology capable of a high speed clock distribution network that efficiently utilizes design resources of independently designed semiconductor circuits.
2. Description of Related Art
FIG. 2 shows an example of a semiconductor integrated circuit device utilizing a high speed clock distribution network of the prior art. In the figure, the reference numeral 101 denotes a phase locked loop (PLL), 102 is a clock distribution line and 103 is a clock buffer. Reference numeral 120 denotes an input clock which is multiplied (increased) N times by the PLL 101 and output frequency to 102 as a multiplied (increased) by N times. The clock pulse multiplied by PLL 101 is amplified in 103 and distributed to each latch (latch and flip-flops are different from each other in the strict sense of the word, however here both latch and flip-flops are represented by the word “latch”) with an equivalent delay. Technical features assuring an equal-length wiring are utilized in order to achieve an equivalent distributed delay.
Once of the distributed clocks 104 is input to the PLL 101 and the PLL 101 functions to obtain an identical phase for the clocks 104 and 120.
FIG. 3 shows the clock distribution network for the semiconductor integrated circuit device of FIG. 2 when added with a macro 130a and 130b. A macro is a separately designed circuit that satisfies specifications for circuits other than the macro (hereafter referred to as mother circuits) as well as interface specifications between macro and mother circuit. As long as these interface specifications are satisfied, the macro can change the mother circuit in various ways.
As one example, the DRAM macro has a memory function to store information by means of capacitance in a circuit described in the 1998 IEEE International Solid-State Circuit Conference Digest of Technical Papers, pp. 72–73.
These macro circuits are sometimes designed as separate items by different designers. One designer may specialize in DRAM macro design while another may specialize in coprocessor macro design. A circuit can then be systematically assembled by combining the macros obtained from these different sources. This method allows utilizing existing macros to design system-level integration devices with high additional value.
In the macro, software IP is used to show design data at the circuit level, and hardware IP is data listing the physical structure of the semiconductor integrated circuit device such as the layout. Hardware IP is more appropriate when high speed operation is required, because performance cannot otherwise be guaranteed when redrafting the physical layout of the circuit.
The clocks distributed to the mother circuit latches are also supplied at an identical phase to the latches in the circuits 121 and 122. The respective macros 130a and 130b distribute the clock pulses input from 121 and 122 to the latches within each macro at an equivalent delay by utilizing the clock buffers 133a and 133b within each macro.
The clock distribution in the semiconductor integrated circuit device of FIG. 3 containing the macros is at a phase identical to the clock phase of 121 and 122 and the latch phase within each mother circuit. However, a delay time Tm is required from 121 and 122 to the input of the clocks to the latches within each macro so that a phase difference (skew) equivalent to the Tm, occurs between the latches within the mother circuit and the latches within the macros.
Further, the Tm within each macro is different so that skew also occurs between macros. This Tm tends to become large when using large scale macros (also called megacells) and the clock skew increases in the semiconductor integrated circuit device using these macros.
In the semiconductor integrated circuit devices of the prior art containing these macros, skew occurs between the clock pulses supplied to the latches within the mother circuit and the clock pulses supplied to the latches within the macro. These clock skews interfere with the high frequency function of the semiconductor integrated circuit device clock frequency so that the semiconductor integrated circuit device cannot be operated at high speed.
A proper delay time for the clock distribution network, from the clock buffer 103 to 121 or 122 calculated during the macro design stage, that takes the Tm into account will resolve this problem but has the drawback that macrocell design cannot be performed independently of mother circuit design.